A complete AI and 3D vision pipeline running on a single embedded SoC, combining real-time object detection with metric depth measurement to lay the foundation for scalable smart camera systems.

Developed by the Deep Vision Consulting team and available now as a ready-to-run starting point, you can get it pre-installed with the Engicam AI.DEV kit or request it for the official Renesas RZ/V2H EVK.

1. The Smart Camera Problem


A growing number of industrial applications share the same fundamental requirement: a system that can identify what it’s looking at and know exactly how far away it is. A warehouse robot needs to recognize a pallet and measure the distance to it. An inspection camera on a production line needs to classify a defect and locate it in three-dimensional space. An autonomous vehicle needs to detect a pedestrian and determine their precise position relative to the chassis.

Until recently, building a system that could both identify objects and measure their 3D position at the edge meant combining together multiple boards, dedicated FPGAs, and external depth sensors: high cost, large form factor, and specialized development effort. What changes when AI inference and 3D reconstruction converge on a single, low-power embedded System-on-Chip?

The result is a complete AI and 3D vision pipeline running on the Renesas RZ/V2H, a vision-focused embedded SoC from Renesas designed for edge applications, combining real-time object detection with metric depth measurement, all executing on a single chip. Deep Vision built this pipeline as a ready-to-run starting point for teams exploring smart camera and embedded 3D vision applications. It’s available today for hands-on evaluation, with details on how to get it at the end of this post.

Renesas RZ/V2H evaluation board with two stereo cameras connected via MIPI CSI-2 interfaces, ready for edge AI and 3D vision processing.
Renesas RZ/V2H evaluation board with two stereo cameras connected via MIPI CSI-2 interfaces, ready for edge AI and 3D vision processing.

What makes this practical and not just technically interesting is the economics behind it. An industrial-grade SoM built around the RZ/V2H, including processor, RAM and flash memory, costs approximately as low as 200€, with low power consumption and a compact footprint. That’s enough to build self-contained smart cameras that detect, classify, and measure objects in real time, deployed in locations where connectivity is unreliable, in volumes where per-unit compute cost is critical, and in applications where latency is measured in milliseconds.

The AI and 3D vision pipeline described in this post is not a finished product, rather it’s a capability pattern, a working, end-to-end system that fuses AI-based object detection with stereo depth measurement running on a single embedded SoC, the RZ/V2H.

Why the RZ/V2H: More Than Just an NPU

Most embedded SoCs targeting vision and AI applications offer a neural processing unit (NPU) as their primary accelerator. The RZ/V2H does too, its DRP-AI accelerator handles neural network inference for tasks like object detection and classification. But NPU-only chips hit a wall when the application demands more than AI.

Comparison diagram showing a typical edge AI SoC with CPU and NPU only, versus the RZ/V2H which adds a DRP accelerator and four MIPI CSI-2 camera inputs.
Comparison diagram showing a typical edge AI SoC with CPU and NPU only, versus the RZ/V2H which adds a DRP accelerator and four MIPI CSI-2 camera inputs.

Stereo depth computation is a case in point. The Semi-Global Matching (SGM) algorithm at the core of classical stereo vision is computationally demanding but poorly suited to NPU architectures, it relies on dynamic programming and cost aggregation patterns that don’t map efficiently to matrix-multiply hardware. Running SGM on the CPU is possible but slow and resource-hungry, leaving little headroom for anything else.

The RZ/V2H addresses this with a second accelerator: the Dynamically Reconfigurable Processor (DRP). The DRP is a programmable hardware fabric optimized for the kind of structured, non-neural compute that stereo matching requires. This is what makes the AI and 3D vision pipeline possible on a single chip, the DRP-AI handles object detection while the DRP simultaneously handles depth computation, and neither competes for the same resource.

Equally important is the RZ/V2H’s native camera connectivity. The SoC provides four MIPI CSI-2 inputs, enough to connect a stereo camera pair (and more) without requiring external multiplexers or bridge chips. Stereo vision demands synchronized image pairs from two cameras; having dedicated, on-chip camera interfaces simplifies the hardware design and reduces both cost and board area.

Without this specific combination, NPU for AI inference, DRP for classical vision acceleration, and multiple MIPI inputs for native multi-camera support, the full AI and 3D vision pipeline cannot run on a single embedded SoC. This is what distinguishes the RZ/V2H from the broader field of edge AI processors. For a detailed technical evaluation of the RZ/V2H’s architecture, accelerators, and individual subsystem benchmarks, see our previously published post: Renesas RZ/V2H Embedded Vision Platform: A Comprehensive Evaluation.

2. Pipeline Architecture: How Five Hardware Blocks Work in Concert


The AI and 3D vision pipeline is designed around the RZ/V2H’s heterogeneous architecture, assigning each processing stage to the hardware block best suited for it. Here’s how the six stages map to the silicon:

  1. Stereo Image Capture (MIPI CSI-2). The pipeline begins with synchronized image pairs captured from two MIPI CSI-2 cameras. Hardware synchronization via the RZ/V2H’s GPIO ports ensures the left and right frames are captured at the same instant, a requirement for accurate depth computation.
  2.  Image Rectification (Cortex-A55 CPU). Raw stereo images are undistorted and rectified on the quad-core Cortex-A55 CPU cluster, aligning the image planes so that corresponding points fall on the same horizontal scanline.
  3. Stereo Matching (DRP). The rectified image pair is processed by the DRP, which runs a hardware-accelerated Semi-Global Matching algorithm to produce a dense disparity map, a pixel-by-pixel encoding of depth information.
  4. AI Inference (DRP-AI) – in parallel with Step 3. Simultaneously, the left camera image is fed to the DRP-AI accelerator, which runs a YOLO object detection model. In our pipeline, this detects and localizes people, but any supported detection or classification model can be substituted.
  5. Data Fusion (Cortex-A55 CPU). The CPU combines the DRP-AI’s detection bounding boxes with the DRP’s disparity map, computing the real-world metric distance to each detected object.
  6. 3D Visualization (Mali-G31 GPU). The onboard GPU renders the depth data as an interactive 3D point cloud via OpenGL ES, viewable and navigable directly on a connected display, no external compute required.
RZ/V2H SoC block diagram with highlighted functional blocks: Cortex-A55 CPU, DRP-AI3, DRP, Mali-G31 GPU, MIPI CSI-2 inputs, and GPIO ports, showing which dedicated hardware are mentioned in the pipeline
RZ/V2H SoC block diagram with highlighted functional blocks: Cortex-A55 CPU, DRP-AI3, DRP, Mali-G31 GPU, MIPI CSI-2 inputs, and GPIO ports, showing which dedicated hardware are mentioned in the pipeline

The critical architectural detail is that steps 3 and 4 execute concurrently. The DRP and DRP-AI are independent accelerators with separate data paths, so stereo matching and AI inference overlap in time rather than competing for the same hardware. This parallelism is what keeps the pipeline running at real-time frame rates within the RZ/V2H’s embedded power envelope.

AI and 3D Vision Pipeline Architecture on the RZ/V2H

Pipeline architecture diagram showing the six processing stages of the AI and 3D vision pipeline, with parallel execution paths through the DRP for stereo matching and DRP-AI for object detection.
Pipeline architecture diagram showing the six processing stages of the AI and 3D vision pipeline, with parallel execution paths through the DRP for stereo matching and DRP-AI for object detection.

3. Full-Pipeline Performance: What the Numbers Actually Show


The numbers below reflect full system-level performance, not isolated accelerator benchmarks. Every figure includes all pipeline stages from stereo capture through AI inference, data fusion, and on-screen result visualization. We tested three configurations at two resolutions to show how the workload distributes across the platform.

At 640 × 360 Resolution

ConfigurationFrame RateCPU Load
3D stereo only (CPU-based SGM)2 fpsCPU saturated
3D stereo only (DRP-accelerated SGM)5 fpsModest CPU load
3D stereo + AI detection (DRP + DRP-AI)5 fpsCPU engaged mainly for detection post-processing and data fusion

At 320 × 180 Resolution

ConfigurationFrame RateCPU Load
3D stereo only (CPU-based SGM)10 fpsCPU saturated
3D stereo only (DRP-accelerated SGM)20 fpsModest CPU load
3D stereo + AI detection (DRP + DRP-AI)10 fps*
CPU engaged mainly for detection post-processing and data fusion

(*) FPS is bounded by object detection running on DRP-AI

When stereo matching runs on the CPU, it saturates the processor and leaves no room for additional workloads. Offloading stereo to the DRP frees the CPU entirely from the heaviest compute task, creating the headroom needed for AI post-processing, data fusion, and application-level logic. Adding AI inference via the DRP-AI does not reduce the stereo frame rate at 640×360, the two accelerators operate in parallel. At 320×180, the combined pipeline reaches 10 fps because the DRP-AI handling object detections becomes the throughput bottleneck.

One technical detail worth noting: the DRP’s current stereo matching implementation outputs 8-bit integer disparity values, which provides good depth resolution at close range, approximately 2 cm at 0.9 meters, but becomes progressively coarser at longer distances. For applications requiring finer depth discrimination at range, the RZ/V2H’s flexible architecture supports alternative stereo approaches, including CPU-based or DRP-AI-accelerated methods that can achieve sub-pixel disparity precision.

4. Fusing AI Detection with Metric Depth


The pipeline takes the bounding boxes produced by the DRP-AI’s YOLO model and maps them into the DRP’s disparity map. For each detected object, the system reads the corresponding disparity values within the bounding box and converts them to a metric distance using the stereo camera’s known baseline and focal length. The result: every detection is annotated with its real-world distance from the camera.

The depth data is also rendered as an interactive 3D point cloud on the onboard GPU, allowing the scene to be explored directly on a connected display: this makes the spatial output tangible and inspectable without any external compute or visualization software.

Combining detection with calibrated distance is what turns a camera from a classification sensor into a spatial measurement tool. Knowing what an object is and where it is, in real-world units, is the foundation for applications that need to act on the physical world: collision avoidance, pick-and-place guidance, spatial occupancy mapping, or proximity-triggered workflows.

Split-screen output from the AI and 3D vision pipeline: left panel shows RGB camera view with a person whose closest body part is detected at 0.28 meters, right panel shows a colorized depth map with blue indicating near surfaces and warm tones indicating distant objects.
Split-screen output from the AI and 3D vision pipeline: left panel shows RGB camera view with a person whose closest body part is detected at 0.28 meters, right panel shows a colorized depth map with blue indicating near surfaces and warm tones indicating distant objects.

5. A Starting Point, Not a Finished Product


This AI and 3D vision pipeline demonstrates that real-time AI inference fused with metric 3D reconstruction is achievable on a single, low-power, cost-effective embedded SoC. The RZ/V2H handles it not through brute force, but through an architecture specifically designed for heterogeneous parallel workloads, DRP-AI for neural inference, DRP for classical stereo vision, GPU for visualization, and four MIPI inputs for native multi-camera support.

But the purpose of this pipeline is not the specific application it shows. Deep Vision built and provides it as a demonstrator and starting point, a working proof that AI + 3D at the edge is a solved problem at the platform level. The open question is what your engineering team will build on this foundation. Whether the target is robotic navigation, industrial inspection, precision agriculture, or any application where knowing what something is and how far away it is matters, the underlying capability pattern is the same and can be adapted through custom computer vision engineering.

How to Get Started

The AI and 3D vision pipeline is available through two paths:

Engicam AI.DEV Kit

The kit ships with three cameras, including two synchronized, pre-calibrated global shutter cameras, and the AI and 3D vision pipeline comes pre-installed. This is the fastest route to a hands-on evaluation: power it on, connect a display, and the pipeline runs out of the box.

link to kit

Renesas RZ/V2H EVK

If you already have or prefer the Renesas evaluation kit, the pipeline is provided for OEMs/ODMs free of charge upon request by filling this form. 

This is the direct path to evaluating what AI and 3D vision at the edge can mean for your next product. The platform is proven. The pipeline is ready. The question is what you’ll build with it.

link to kit
Related Posts